In general, a semiconductor memory device such as Dynamic Random Access Memory (DRAM) is driven by a row address and a column address externally provided. FIG. 1 is a block diagram of a conventional semiconductor memory device.
The conventional semiconductor memory device includes a global column address controller 10, a clock controller 20, a bank column address controller 30, a command controller 40, a column address enable controller 50 and a Column Address (CA) latch unit 60.
The global column address controller 10 is provided with an address (ADD) pad 11, an ADD buffer 12, an ADD latch 13, an ADD selector 14, an Additive Latency (AL) shift register 15, a CA selector 16, and a CL shift (CL+1(+3) shift register 17.
The clock controller 20 is provided with a clock (CK/CKB) pad 21 and a clock (CLK/CLKB) buffer 22.
The bank column address controller 30 is equipped with a Bank Address (BA) pad 31, an ADD buffer 32, an ADD latch 33, an ADD selector 34, an AL shift register 35, a CL shift (CL+1(+3) shift register 36, a CA selector 37, and a BA decoder 38.
The command controller 40 is composed of a command (CMD) pad 41, a CMD buffer 42, a CMD latch 43, a CMD decoder 44, AL shift registers 45 and 46, and a CL shift register 47. The column address enable controller 50 is provided with a column address enable (YAE) signal generator 51, a YAE signal delay unit 52, and a YAE signal decoder 53. The CA latch unit 60 is provided with a CA latch 61.
FIG. 2 is a detailed circuit diagram of the BA decoder 38 shown in FIG. 1.
The BA decoder 38 is composed of a plurality of inverters IV1 to IV6 and a plurality of NAND gates ND1 to ND4 to logically multiply signals input thereto. As illustrated, the BA decoder 38 is applied to a semiconductor memory device having a 4-bank structure.
More specifically, the NAND gate ND1 NAND-operates a bank address BA0 inverted by the inverter IV1 and a bank address BA1 inverted by the inverter IV2. The NAND gate ND2 NAND-operates the bank address BA0 and the bank address BA1 inverted by the inverter IV2. The NAND gate ND3 NAND-operates the bank address BA0 inverted by the inverter IV1 and the bank address BA1. The NAND gate ND4 NAND-operates the bank addresses BA0 and BA1.
The inverter IV3 inverts an output of the NAND gate ND1 to provide a bank column address CBA<0> . The inverter IV4 inverts an output of the NAND gate ND2 to output a bank column address CBA<1> . The inverter IV5 inverts an output of the NAND gate ND3 to provide a bank column address CBA<2> . The inverter IV6 inverts an output of the NAND gate ND4 to provide a bank column address CBA<3>.
The following is an operation description of the conventional semiconductor memory device having the configuration as mentioned above, which is made with reference to an operation timing diagram shown in FIG. 3. In the operation timing diagram of FIG. 3, it is assumed that in Double Data Rate Two Synchronous DRAM (DDR2 SDRAM) AL is “2,” CL is “6” and Burst Length (BL) is “4.”
The column address is controlled by the global column address controller 10 and the bank column address controller 30. The global column address controller 10 serves to control a global column address for each bank to access (read or write) data of a sense amplifier. The bank column address controller 30 is to control a bank column address having information of a bank to be selected. Here, the bank column address implies a column address enable signal to latch the bank selected according to the global column address.
Each column address is generated in an identical sequence under the control of the clock controller 20 and the command controller 40. The clock buffer 22 buffers clocks (CLK and CLKB) provided from the clock pad 21 to provide the same as an overall synchronizing signal within a chip.
An address applied to the ADD pad 11 is fed to the ADD latch 13 via the ADD buffer 12. A bank address at the BA pad 31 is delivered to the ADD latch 33 via the ADD buffer 32. At this time, the ADD latches 13 and 33, as shown in A(A′) of FIG. 3, outputs the addresses to the ADD selectors 14 and 34 in synchronism with a falling edge of a clock CLK provided from the clock buffer 22, respectively.
Thereafter, when a write command WT or read command RD is applied to the CMD pad 41, it is delivered to the ADD selectors 14 and 34, in which the column addresses are queued, in synchronism with the falling edge of the clock CLK, as in the address.
Further, as depicted in B(B′) of FIG. 3, a signal is output to the AL shift registers 15 and 35 to perform the AL and CL functions depending on Mode Register Set (MRS) that is set by latching the column address.
At this time, Read Latency (RL) becomes AL+CL and Write Latency (WL) becomes RL-1 in DDR2 spec, which leads to AL+CL−1. In the read mode, the column address is shifted by the clock number of AL value, as in D(D′) of FIG. 3, and the clock corresponding to CL value is shifted by the CL clock number in a block that outputs data to a DQ pad.
When the read command is input, a read command signal RDP is output through the CMD decoder 44 followed by the same AL shift register 45 as in the column address. The column addresses through the AL shift registers 15 and 35 are applied to the CA selectors 16 and 37, which take the read command signal RDP and provide read column addresses, as in E(E′) of FIG. 3.
On the other hand, in the write mode, the column address is shifted by WL and further shifted by BL/2. The DDR2 is characterized by 4-bit pre-fetch. Here, in order to perform the 4-bit pre-fetch, 2-clock is required where BL=4 and 4-clock where BL=8, by conducting the fetch at the rising edge and falling edge of every clock.
In the write mode, data is input after WL, and therefore, more time is needed to fetch the data in order to make the data internally aligned. By further shifting the data by that time, the write column address can be synchronized with the data on the Global Input/Output (GIO) bus at the same timing. Accordingly, the write column address, as in D(D′) of FIG. 3, is shifted by AL+CL+1 where BL=4 (2-clock) and AL+CL+3 where BL=8 (4-clock).
The write command is shifted by the same clock number via the CMD decoder 44 to output the write command signal WTP. The write command signal WTP of the CMD decoder 44 is then applied to the CA selectors 16 and 37 to provide write column addresses, as in E(E′) of FIG. 3.
Among the output addresses, the column address as in E of FIG. 3 is globally delivered to all banks; and the bank column address as in E' of FIG. 3 is decoded by the BA decoder 38 and a signal as in CBA of FIG. 3 is then output to only a selected bank. The output signal CBA of the BA decoder 38 is latched by the CA latch 60 and then delivered to the selected bank.
Meanwhile, the YAE signal generator 51 combines the read command signal RDP, the write command signal WTP and the CAS signal ICASP (where BL=8). And the YAE signal delay unit 52 delays an output signal of the YAE signal generator 51 for a certain time. The YAE signal decoder 53 decodes a bank information signal BBY<0:3> and an output signal of the YAE signal delay unit 52 to provide a column address enable signal YAE<0:3> to the selected bank.
At this time, during the write operation in the selected bank, the data transferred from the GIO bus is stored in a corresponding cell according to an enable of a write driver (WTDRV). During the read operation in the selected bank, a developed signal of data transferred through local input/output buses SIO and LIO is amplified in a bit line sense amp depending on an enable of an Input/Output Sense Amp (IOSA) and then fed to the GIO bus. Thus, it is required to maintain a constant interval with the column address in order to secure a margin during the write and read operations. For this, the YAE signal delay unit 52 delays the column address enable signal YAE for a certain time.
The column address is delivered after the row address is provided to the bank together with an active command. This elapsed time is defined as tRCD [Row Address Strobe (RAS) to CAS Delay], which may be 15 ns as 6-clock where CL=6. This means time that the data of the sense amp can be accessed by the column address after the word line is enabled by the row address and thus the sense amp is sufficiently operated. Such tRCD time is used as an index to determine the performance, wherein the performance is judged to be excellent as it is shorter.
Therefore, there is no problem if tRCD margin is sufficient, but there is problem in delaying the externally applied column address if it is deficient.
In addition, there is a recent trend to require low latency products with tRCD decreased by 1 clock in comparison with the spec. Accordingly, although there is tRCD margin in the spec, lack of margin may happen due to operation under such tRCD state decreased by 1 clock.